Contents
Getting the Files
Copying to your library
To use, simply grab the file, and untar it into your cadence working directory with the following command
tar fxvz /home/cadence/olin_padframe.tar.gz
Then close Cadence and add the library to your cds.lib file by adding the lines
DEFINE olinpad40 ./olinpad40 DEFINE olinpad60 ./olinpad60 DEFINE olinpad80 ./olinpad80
Referencing my padframe
If you don't want to copy it, just add the following lines to your cds.lib file:
DEFINE olinpad40 /home/cadence/olinpad40 DEFINE olinpad60 /home/cadence/olinpad60 DEFINE olinpad80 /home/cadence/olinpad80
Changing DRC rules
The padframe is complex and needs a few tweaks to the stock Cadence/NCSU-CDK DRC ruleset to come into compliance with MOSIS. To do this, do the following when you are doing a DRC that includes anything from the padframe library. (You can use this all the time, as the rules should be fine for any part of the AMI C5N flow.)
Start DRC through Verify > DRC ...
Replace the Rules file with /home/cadence/olin_ami06.rul
Uncheck the box next to Rules Library
Now, your DRC window should look like:
The 40-pin package
This is a top view of the 40-pin dual in-line package (DIP) in which your chip will packaged and returned.
We do not have drawings for the 60 and 80 pin packages.
How to use the pads and padframe
Pads facilitate the interface between the macroscopic world of BNC cables, lab benches, and logic analyzers and the microscopic world of the core of an integrated circuit. Output pads provide buffers with current driving capability sufficient to drive off-chip loads in a reasonable amount of time. Input pads provide some measure of protection against zapping your thin gate oxides with an electrostatic discharge. (Please note, however, that the pad ESD protection is no substitute for careful ESD handling practices.)
That image above gives an overall picture of how the pad frame (40 pin) is arranged and the number of the pin to which each bonding pad will be connected when the chip is packaged. There are a total of 40 pads with a usable chip area of around 3974 lambda by 3974 lambda (1191 microns in each direction). The four corner pads (i.e., those numbered 5, 15, 25, and 35) are "reserved." Pin 5 is a Bias voltage pin that is normally used to bias "analog" pads. It has the same basic protection structure as the inpad. Bias is routed into the core all around the pad frame and you may use it for a digital input connected to gates. Pin 15 is ground. Pin 25 is Vdd for the core of the chip, Pin 35 is Vdd for the pad frame. Ground and core Vdd (CVdd) are available all around the pad frame in either metal1 or metal2. You are free specify the type of pad that will go into each of the nine locations along the top, bottom, left, and right of the pad frame.
The 40-pin padframe
There is a basic 40-pin Tiny Chip padframe in the cellview chip inside the library olinpad40. Personally, I'd create a new cellview in your project called something like final_design_with_padframe. I would open the demo padframe, and copy all the cells into your final_design_with_padframe. Then, instantiate your top-level final design inside the pad.
Initially, the padframe consists of just bonding pads. These pads are not even hooked up to the internal part of the chip area. You need to change the ones you need to use! The pad types are described below. To change a pad along the top, bottom, left, or right edge of the pad frame, you can do two things:
Delete it, and instantiate the pad you really want. To get it to be the right orientation, utilize the Rotate command (not the flip command) until it lines up right.
Even easier, hit q to modify the properties of the cell, such as ahte blankpad, and change the cellview to a different pad, one of barepad, inorpad, inpad, iopad.
Connecting to the pads
If you zoom way in to the inner edge of a pad, you can see several 7 different metal 1 wires coming from the pad and the pad ring. These are actually labeled, so go ahead and turn on labels by hitting 'e' (or select Options / Display) and toggling the Pin Names on.
You will see gnd! vdd! Bias! xxx Bias! vdd! gnd! in that order. xxx is the name of the type of pad (described below) and is the wire actually connected to the pad. So, if you want to get Vdd!, just connect to the Vdd! conveniently located at the edge of every pad. Awesome.
The Pad Set
Here, we'll talk about each of the pads available to you. You should instantiate them as necessary.
Bonding pad (blankpad)
This is just an island of metal. Do not use in your final padframe hierarchy.
Bare pad (barepad)
Input or Output
The barepad is a bonding pad with a metal wire to the core of the chip. This pad has NO ESD PROTECTION, and so should be used with caution, and then only for nodes connected to a lot of source/drain regions. This pad is useful for providing additional power and ground pins (or some other supply voltage) and for measuring small currents without having any leakage from protection structures. This one is DEFINITELY NOT for inputs tied exclusively to gates!
Inor pad (inorpad)
Input or Output
The inor pad is a bonding pad with a metal wire to the core of the chip and with "clamping" ESD protection. There are four reversed biased diodes to the substrate, which will prevent the input from going more than one diode-drop below ground. The same is done on the high side, with three forward-biased diodes to Vdd. This prevents the input from going more than one diode-drop above Vdd. This pad is suitable for connecting to source/drains. It's probably not a good idea to use this for inputs connected exclusively to gates.
This pad can be used for input or output.
Input Pad (inpad)
Input only
The inpad is an inorpad with a series poly resistor between the bonding pad and the clamping circuitry. There is a reversed biased diode to the substrate, which will prevent the input from going more than one diode-drop below ground. The diode and PNP prevent the end of the resistor nearest the core of the chip from going more than a diod-drop outside of the power supply. The resistor allows a voltage drop between the bonding pad and the clamping circuitry. This pad is suitable protection for gates. Please note that no ESD protection circuitry is a substitute for careful chip handling practices.
IO pad (iopad)
Digital Input or Output
The iopad is a bidirectional digital I/O pad. It comprises a tristate buffer and the ESD protection structures of an inpad. The pad takes a control signal that determines whether or not the tristate buffer drives the output. Please note that if you intend to short the OUT and OUT lines together, whatever drives that line from the inside of your chip will "see" the RC load of the bonding pad until the point at which the tristate buffer starts driving. It might be advisable to put a small tristate buffer or transmission gate between the IN and OUT lines in this situation to decouple the pad from the line.
This pad can be used for input or output.